Package-on-package (PoP) structures have been developed for applications such as cellular telephones and other portable devices in which circuit board space must be conserved. The top package is typically a memory package whereas the bottom package is commonly a processor package. Package-on-package technology has proven to be quite popular as compared to other approaches such a stacked-die circuit. For example, a manufacturer can readily substitute different memory packages in a PoP circuit, which thus lowers costs as opposed to being tied to a particular memory. Moreover, the top and bottom packages may be tested independently. In contrast, a bad die in a stacked-die design requires rejection of the remaining good die.
Although the packaging of integrated circuits using PoP structures is thus quite popular, challenges remain in this packaging process. For example, as technology advances, users desire a reduced thickness or height to the PoP stack. But despite the technological advances in the PoP arts, obstacles remain with regard to reducing the PoP stack height. The problems with regard to reducing the package height may be better understood with reference to FIGS. 1A and 1B. FIG. 1A shows a conventional PoP stack 100. To construct PoP 100, a bottom package die 105 is first flip-chip mounted to a bottom package substrate 110 and encapsulated with a mold compound layer 108. Vias are then formed in molding compound layer 108 such as through laser ablation to expose lower solder balls on bottom package substrate 110. Corresponding upper solder balls on a top package substrate 120 are then received in the vias, whereupon a reflow process forms solder joint interconnects 115 from the reflowed upper and lower solder balls to electrically couple top package substrate 120 to bottom package substrate 110.
Because of the through-mold-via process used to form PoP 100, there is a gap 140 between a lower surface of top package substrate 120 and an upper surface of mold compound layer 108. Gap 140 thus increases a PoP stack height for PoP 100. To achieve a reduced stack height that does not suffer from gap 140, an alternative PoP architecture has been developed that may be denoted as a molded-embedded (ME) PoP 130 as shown in FIG. 1B. In ME-PoP 130, mold compound 108 is applied after top package substrate 120 and lower package substrate have been joined through interconnects 115. In this fashion, ME-PoP 130 does not have a gap 140 between the bottom surface of top package substrate 120 and an upper surface for mold compound 108. Me-PoP 130 thus has a reduced height as compared to PoP 100. But regardless of which architecture is chosen, it can be seen that the bottom surface of top package substrate 120 is always above the top surface of bottom die 105 since top package substrate 120 covers bottom die 105. In other words, top package substrate 120 is stacked with regard to bottom die 105. The thickness of top package substrate 120 is thus a direct factor in the height of the overall PoP stack.
If the thickness of the top package substrate in a conventional PoP can be thinned by some number of microns, the height of the PoP is then reduced by the same number of microns. Similarly, a reduction in the thickness for the bottom package substrate also reduced the PoP stack height. The substrates for the top and bottom packages have thus been progressively thinned to obtain reduced PoP stack height. But current state-of-the-art organic substrates can be thinned to no less than approximately 80 to 90 microns. If the substrates are made any thinner than this minimum thickness, unacceptable warping occurs. So the minimum package substrate thickness for the top and bottom package substrate acts to thwart further advances in PoP stack height reduction.
Accordingly, there is a need in the art for improved PoP circuits having reduced height while still having robust protection against substrate warpage.